Lateral InAs/Si p-Type Tunnel FETs Integrated on Si—Part 1: Experimental Devices-Reference-Cited by-同舟云学术

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Lateral InAs/Si p-Type Tunnel FETs Integrated on Si—Part 1: Experimental Devices

Published:2016-11 Issue:11 Volume:63 Page:4233-4239
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Moselund Kirsten Emilie^ORCID,Cutaia Davide,Schmid Heinz,Borg Mattias,Sant Saurabh,Schenk Andreas,Riel Heike

Funder

EU FP7 project E2SWITCH

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/7592488/07581026.pdf?arnumber=7581026

Cited by 33 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Study and analysis of the effects of trap assisted tunneling on the sensing performance of InAs/Si hetero juncture TFET based biosensor;Physica Scripta;2024-08-13

2. InAs Raised Buried Oxide SOI-TFET with N-type Si_1-xGe_x Pocket for Low-Power Applications;Nanoelectronic Devices and Applications;2024-06-26

3. A Novel Fin-Shape Double-Gate GaAs p-MOSFET With Intrinsic Source and Enhanced Switching Performance;IEEE Transactions on Dielectrics and Electrical Insulation;2024-06

4. Investigation of the Electrical Parameters in a Partially Extended Ge-Source Double-Gate Tunnel Field-Effect Transistor (DG-TFET);Journal of Electronic Materials;2024-03-26

5. A non-quasi-static model for nanowire gate-all-around tunneling field-effect transistors;Chinese Physics B;2023-05-01

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