A scalable high-speed current-mode winner-take-all network for VLSI neural applications-Reference-Cited by-同舟云学术

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A scalable high-speed current-mode winner-take-all network for VLSI neural applications

Published:1995-05 Issue:5 Volume:42 Page:289-291
ISSN:1057-7122
Container-title:IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Smedley S.,Taylor J.,Wilby M.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx4/81/8753/00386164.pdf?arnumber=386164

Cited by 18 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Winner-Take-All and Loser-Take-All Circuits: Architectures, Applications and Analytical Comparison;Chips;2023-11-08

2. Training Winner-Take-All Simultaneous Recurrent Neural Networks;IEEE Transactions on Neural Networks;2007-05

3. 1-V bulk-driven CMOS analog programmable winner-takes-all circuit;Analog Integrated Circuits and Signal Processing;2006-06-27

4. Soft-max circuit design with adjustable gain;IEE Proceedings - Circuits, Devices and Systems;2006

5. High-reliability programmable CMOS WTA∕LTA circuit of O(N) complexity using a single comparator;IEE Proceedings - Circuits, Devices and Systems;2004

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