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Impact of Interface Traps in Floating-Gate Memory Based on Monolayer MoS

  • Published:2022-11 Issue:11 Volume:69 Page:6121-6126
  • ISSN:0018-9383
  • Container-title:IEEE Transactions on Electron Devices
  • language:
  • Short-container-title:IEEE Trans. Electron Devices

Author:

Giusi G.1ORCID,Marega G. M.2,Kis A.2ORCID,Iannaccone G.3ORCID

Affiliation:

1. Engineering Department, University of Messina, Messina, Italy

2. Institute of Electrical and Microengineering, École Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland

3. Dipartimento di Ingegneria dell’Informazione, Università di Pisa, Pisa, Italy

Funder

European Commission through the QUEFORMAL Project

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Exploring new logic devices: Unlocking potential with floating-gate transistor;Applied Physics Reviews;2024-08-09

2. Design of MoS2 based Inverter Circuits considering Interface Trap effect;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

3. The case for hybrid analog neuromorphic chips based on silicon and 2D materials;2023 International Electron Devices Meeting (IEDM);2023-12-09

4. A large-scale integrated vector–matrix multiplication processor based on monolayer molybdenum disulfide memories;Nature Electronics;2023-11-13

5. How to Achieve Large-Area Ultra-Fast Operation of MoS2 Monolayer Flash Memories?;IEEE Nanotechnology Magazine;2023-10
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