Analytical Modeling of Potential Barrier for Charge Transfer in Pinned Photodiode CMOS Image Sensors
Author:
Affiliation:
1. College of Computer, National University of Defense Technology, Changsha, China
2. State Key Laboratory of Intense Pulsed Radiation Simulation and Effect, Northwest Institute of Nuclear Technology, Xi’an, China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/9901396/09874861.pdf?arnumber=9874861
Reference26 articles.
1. A Sub-0.5 Electron Read Noise VGA Image Sensor in a Standard CMOS Process
2. Charge transfer speed analysis in pinned photodiode CMOS image sensors based on a pulsed storage-gated method;pelamatti;Proc Solid-State Device Research Conf,2015
3. Experimental Analysis of Lag Sources in Pinned Photodiodes
4. no image lag photodiode structure in the interline ccd image sensor;teranishi;1982 International Electron Devices Meeting,1982
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1. Incomplete charge transfer in CMOS image sensor caused by Si/SiO2 interface states in the TG channel;Journal of Semiconductors;2023-11-01
2. Mathematical model of potential distribution in a pinned photodiode of an indirect time of flight CMOS image sensor;Applied Optics;2023-03-20
3. The effect of photodiode shape on pinning potential for charge transfer in CMOS image sensors;Microelectronics Journal;2023-01
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