A Multilayer Neural Accelerator With Binary Activations Based on Phase-Change Memory

Author:

Bertuletti Marco1ORCID,Muñoz-Martín Irene1ORCID,Bianchi Stefano1ORCID,Bonfanti Andrea G.1ORCID,Ielmini Daniele1ORCID

Affiliation:

1. Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Politecnico di Milano, Milan, Italy

Funder

Electronics Components and Systems for European Leadership (ECSEL) Joint Undertaking

European Union’s Horizon 2020 Research and Innovation Program and France, Belgium, Czech Republic, Germany, Italy, Sweden, Switzerland, and Turkey

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Reference39 articles.

1. A 4M Synapses integrated Analog ReRAM based 66.5 TOPS/W Neural-Network Processor with Cell Current Controlled Writing and Flexible Network Architecture

2. Binarized neural networks: Training deep neural networks with weights and activations constrained to +1 or ?1;courbariaux;arXiv 1602 02830 [cs],2016

3. In-memory computing with resistive switching devices

4. The StrongARM Latch [A Circuit for All Seasons]

5. A CMOS-integrated compute-in-memory macro based on resistive random-access memory for ai edge devices;xue;Nature Electron,2021

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