Engineered Vertically Stacked NSFET Charge-Trapping Synapse for Neuromorphic Applications-Reference-Cited by-同舟云学术

Engineered Vertically Stacked NSFET Charge-Trapping Synapse for Neuromorphic Applications

Published:2023-12-04 Issue:12 Volume:5 Page:7079-7086
ISSN:2637-6113
Container-title:ACS Applied Electronic Materials
language:en
Short-container-title:ACS Appl. Electron. Mater.

Author:

Raza Ansari Md. Hasan¹,Navlakha Nupur²,El-Atab Nazek¹^ORCID

Affiliation:

1. Electrical and Computer Engineering, Computer, Electrical and Mathematical Science and Engineering (CEMSE) Division, King Abdullah University of Science and Technology (KAUST), Thuwal 23955-6900, Saudi Arabia

2. Microelectronics Research Center, Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas78758, United States

Funder

King Abdullah University of Science and Technology

Publisher

American Chemical Society (ACS)

Subject

Materials Chemistry,Electrochemistry,Electronic, Optical and Magnetic Materials

Link

https://pubs.acs.org/doi/pdf/10.1021/acsaelm.3c01420

Reference32 articles.

1. Jerry, M.; Chen, P.Y.; Zhang, J.; Sharma, P.; Ni, K.; Yu, S.; Datta, S. In Ferroelectric FET Analog Synapse for Acceleration of Deep Neural Network Training, 2017 IEEE International Electron Devices Meeting (IEDM); IEEE, 2017; Vol. 6, pp 6.2.1–6.2.4.

2. Emerging neuromorphic devices

3. Opportunities for neuromorphic computing algorithms and applications

4. Prospect and challenges of analog switching for neuromorphic hardware

5. Memory devices and applications for in-memory computing

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