Charge-Trapping-Induced Compensation of the Ferroelectric Polarization in FTJs: Optimal Conditions for a Synaptic Device Operation
Author:
Affiliation:
1. Polytechnic Department of Engineering and Architecture (DPIA), University of Udine, Udine, Italy
2. IFOX, Helmholtz-Zentrum Berlin, Berlin, Germany
3. Institut für Physik, Humboldt-Universität zu Berlin, Berlin, Germany
Funder
European Union through the BeFerroSynaptic Project
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/9802454/09781803.pdf?arnumber=9781803
Reference30 articles.
1. The Quantum Metal Ferroelectric Field-Effect Transistor
2. Stabilization of negative capacitance in ferroelectric capacitors with and without a metal interlayer
3. Modelling and design of FTJs as high reading-impedance synaptic devices
4. Modeling and Design of FTJs as Multi-Level Low Energy Memristors for Neuromorphic Computing
5. Experimental study on polarization-limited operation speed of negative capacitance FET with ferroelectric HfO2;kobayashi;IEDM Tech Dig,2016
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