Asymmetric U-Shaped-Gated TFET for Low-Power Ana–Digi Applications at Sub-7-nm Technology Node: A Simulation-Based Optimization Study
Author:
Affiliation:
1. Department of Radio Physics and Electronics, University of Calcutta, Kolkata, India
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/9926983/09903406.pdf?arnumber=9903406
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. III-V material-based junction-free L-shaped gate normal line tunneling FET for improved performance;Semiconductor Science and Technology;2024-08-07
2. Comparative analysis of performance and its stability against real-time non-ideal conditions between DG-TFET sensor and its MOS equivalent for a range of biomolecule detection: a design perspective;AEU - International Journal of Electronics and Communications;2024-04
3. Novel Reconfigurable Field-Effect Transistor With Arch-Shaped Gate to Improve On-State Current;IEEE Transactions on Electron Devices;2023-10
4. Study on linearity and harmonic distortion for a unique U-TFET in low-power analog/RF applications: The role of channel epilayer thickness;AEU - International Journal of Electronics and Communications;2023-08
5. A new line tunneling SiGe/Si iTFET with control gate for leakage suppression and subthreshold swing improvement;Discover Nano;2023-07-28
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