Defect-Based Empirical Model for On-State Degradation in Sub-20-nm DRAM Periphery pFETs Under Arbitrary Condition-Reference-Cited by-同舟云学术

Defect-Based Empirical Model for On-State Degradation in Sub-20-nm DRAM Periphery pFETs Under Arbitrary Condition

Published:2022-12 Issue:12 Volume:69 Page:6669-6675
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Wang Da¹^ORCID,Zhou Longda¹,Xue Yongkang¹^ORCID,Ren Pengpeng¹,Zhang Lining²^ORCID,Li Xiong³,Liu Xiangli³,Wang Jianping³,Wu Blacksmith³,Ji Zhigang¹^ORCID,Wang Runsheng²^ORCID,Cao Kanyu³,Huang Ru²

Affiliation:

1. National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Shanghai Jiaotong University, Shanghai, China

2. School of Integrated Circuits, Peking University, Beijing, China

3. ChangXin Memory Technologies, Hefei, China

Funder

National Key Research and Development Program of China

National NSF of China

111 Projects

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/9967813/09918651.pdf?arnumber=9918651

Reference35 articles.

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5. Overcoming the reliability limitation in the ultimately scaled DRAM using silicon migration technique by hydrogen annealing