Research on the yield optimization scheme of ESD devices based on FOPLP packaging-Reference-Cited by-同舟云学术

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Research on the yield optimization scheme of ESD devices based on FOPLP packaging

Published:2022-08-10 Issue: Volume: Page:
ISSN:
Container-title:2022 23rd International Conference on Electronic Packaging Technology (ICEPT)
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Author:

Li Yuhong¹,Gao Chenshan¹,Hu Jinjin²,Liu Jianhui³,Zhang Qiangbo²,Liu Lei²,Song Guanqiang¹,Jiang Jing¹,Ye Huaiyu⁴

Affiliation:

1. Sky Chip Interconnection Technology CO., LTD,Product Research and Development,Shenzhen,China

2. Sky Chip Interconnection Technology CO,. LTD,Pingxi Preparatory Team,Shenzhen,China

3. Sky Chip Interconnection Technology CO., LTD,R&D Design Department,Shenzhen,China

4. Southern University of Science and Technology,Chongqing University,Shenzhen,China

Funder

Shenzhen Fundamental Research Program

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9872527/9872536/09872551.pdf?arnumber=9872551

Reference6 articles.

1. Modeling and experimentation of creep-fatigue and failure of low-profile quad flat package under thermal cycle

2. Development of 500mm×500mm Fan-out panel level packaging for heterogeneous chip integration

3. High Density Interconnect Processes for Panel Level Packaging

4. Process Development and Failure Analysis for Chip-Last Panel Level Fan-out Packaging (PLP)

5. Mechanism of Moldable Underfill (MUF) Process for RDL-1^st Fan-Out Panel Level Packaging (FOPLP)

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