Serial-parallel FFT array processor
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Signal Processing
Link
http://xplorestaging.ieee.org/ielx4/78/5272/00205760.pdf?arnumber=205760
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. An optimized reconfigurable algorithm for FPGA architecture oriented IoT applications;Cognitive Systems Research;2018-12
2. A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation;ACM SIGARCH Computer Architecture News;2014-12-09
3. FPGA implementation of a novel architecture for performance enhancement of Radix-2 FFT;ACM SIGARCH Computer Architecture News;2012-05-31
4. Distributed arithmetic realisation of cyclic convolution and its DFT application;IEE Proceedings - Circuits, Devices and Systems;2005
5. A novel algorithm for computing the 2D split-vector-radix FFT;Signal Processing;2004-03
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