FPGA implementation of a novel architecture for performance enhancement of Radix-2 FFT-Reference-Cited by-同舟云学术

FPGA implementation of a novel architecture for performance enhancement of Radix-2 FFT

Published:2012-05-31 Issue:2 Volume:40 Page:28-32
ISSN:0163-5964
Container-title:ACM SIGARCH Computer Architecture News
language:en
Short-container-title:SIGARCH Comput. Archit. News

Author:

Giri Nishant Kumar¹,Sinha Amitabha¹

Affiliation:

1. West Bengal University of Technology, Salt lake City, Kolkata, India

Abstract

This paper presents a novel architecture for the enhancement of performance of compute intensive Fast Fourier Transform (FFT) algorithm which is common in many signal processing applications. The proposed architecture exhibits faster response time compared to radix-2 'Single-path Delay Feedback (SDF)' architecture and 'radix-2 Multi-path Delay Commutator (MDC)' architecture. The architecture was simulated using Modelsim and was implemented on Xilinx Virtex 4 FPGA.

Publisher

Association for Computing Machinery (ACM)

Link

https://dl.acm.org/doi/pdf/10.1145/2234336.2234341

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