Exploration on Reusability of Universal Verification Methodology
Author:
Affiliation:
1. Kalasalingam Academy of Research and Education,Department of ECE,Krishnankoil,India
2. Ramco Institute of Technology,Department of ECE,Rajapalayam,india
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9823381/9823413/09823570.pdf?arnumber=9823570
Reference10 articles.
1. A Comprehensive Investigation of Universal Verification Methodology(UVM) Standard for Design Verifiction;qamar;ICSCA 2020 February 1821z 2020 Langkawi Malaysia,0
2. A RSIC CPU Oriented Reusable Functional Verification Platform Based on UVM;xie;Acta Scientiarum Naturalium Universitatis Pekinensis,2013
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