Design of a 3-V 300-MHz low-power 8-b/spl times/8-b pipelined multiplier using pulse-triggered TSPC flip-flops-Reference-Cited by-同舟云学术

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Design of a 3-V 300-MHz low-power 8-b/spl times/8-b pipelined multiplier using pulse-triggered TSPC flip-flops

Published:2000-04 Issue:4 Volume:35 Page:583-592
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Jinn-Shyan Wang ,Po-Hui Yang ,Duo Sheng

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/18159/00839918.pdf?arnumber=839918

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Performance Evaluation of Pulse Triggered Flip-Flops in 32 nm CMOS Regime;2023 2nd International Conference on Applied Artificial Intelligence and Computing (ICAAIC);2023-05-04

2. Investigation on Power Supply Scaling Effects on the Performance of PET/NET TSPC-DATA-Flip Flops at Wide Range of Operating Temperatures;2022 IEEE 3rd International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA);2022-12-15

3. An automatic mode low-jitter pulsewidth control loop with broadband operation frequency;Microelectronics Journal;2016-12

4. Benchmarking of DPL-based 8b × 8b novel wave-pipelined multiplier;International Journal of Electronics Letters;2016-04-21

5. Dynamic-static hybrid near-threshold-voltage adder design for ultra-low power applications;IEICE Electronics Express;2015

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