Study on Voltage Influence on FPGA-Based Time-to-Digital Converters
Author:
Affiliation:
1. University of Science and Technology of China,Department of Modern Physics,Hefei,China
Funder
National Natural Science Foundation of China (NSFC)
Chinese Academy of Science
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10175865/10175876/10175889.pdf?arnumber=10175889
Reference21 articles.
1. Sharing, Protection, and Compatibility for Reconfigurable Fabric with {AmorphOS};khawaja,0
2. A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance
3. A 128-Channel, 710 M Samples/Second, and Less Than 10 ps RMS Resolution Time-to-Digital Converter Implemented in a Kintex-7 FPGA
4. FPGAhammer: Remote Voltage Fault Attacks on Shared FPGAs, suitable for DFA on AES
5. On the Commonly-Used Incorrect Visual Representation of Accuracy and Precision
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1. Calculation of the Worst-Case Voltage Noise for a Power Distribution Network Based on Ramp Current;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-06
2. Design of A High Performance Time-to-Digital Converter with Zero Dead Time on Xilinx FPGA;2024 IEEE International Instrumentation and Measurement Technology Conference (I2MTC);2024-05-20
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