A High-speed Low-power Sense Amplifier for the RRAM Array with Multi-level Reading Function using 130-nm Technology
Author:
Affiliation:
1. Technical University of Munich,Chair of Micro- and Nanosystems Technology,Germany
2. University of Rostock,Lehrstuhl Integrierte Systeme,Germany
Funder
Ministry of Education
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10382705/10382711/10382824.pdf?arnumber=10382824
Reference9 articles.
1. Resistive Random Access Memory (RRAM): an Overview of Materials, Switching Mechanism, Performance, Multilevel Cell (mlc) Storage, Modeling, and Applications
2. Impact of coupling capacitance on read operation of RRAM devices in 1D1R crossbar architectures
3. SRIF: Scalable and Reliable Integrate and Fire Circuit ADC for Memristor-Based CIM Architectures
4. The StrongARM Latch [A Circuit for All Seasons]
5. Kickback noise reduction techniques for CMOS latched comparators
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