Co-Design for Low Warpage and High Reliability in Advanced Package with TSV-Free Interposer (TFI)
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7998598/7999654/07999787.pdf?arnumber=7999787
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Double-sided silicon vias (DSSVs) interconnection for large-sized interposer fabrication;Microelectronics International;2023-01-20
2. Recent Advances and Trends in Multiple System and Heterogeneous Integration With TSV Interposers;IEEE Transactions on Components, Packaging and Manufacturing Technology;2023-01
3. Multiple System and Heterogeneous Integration with TSV-Interposers;Chiplet Design and Heterogeneous Integration Packaging;2023
4. Functional Demonstration of < 0.4-pJ/bit, 9.8 μm Fine-Pitch Dielet-to-Dielet Links for Advanced Packaging using Silicon Interconnect Fabric;2022 IEEE 72nd Electronic Components and Technology Conference (ECTC);2022-05
5. 2.5D IC Integration;Semiconductor Advanced Packaging;2021
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