Backside Optical I/O Module for Si Photonics Integrated with Electrical ICs Using Fan-Out Wafer Level Packaging Technology
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8415930/8429093/08429640.pdf?arnumber=8429640
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Silicon Photonics Under Siege: Unveiling Security Vulnerabilities Against SAW;2024 IEEE Research and Applications of Photonics in Defense Conference (RAPID);2024-08-14
2. Physical assurance for photonics devices;Photonic Instrumentation Engineering XI;2024-03-11
3. Solutions for Process Challenges on Fan-Out Wafer Level Packaging of Electronic-Photonic Integration;2023 IEEE 25th Electronics Packaging Technology Conference (EPTC);2023-12-05
4. Exploration of a neural-network-based joint method of mapping and wavelength assignment in optical network-on-chip;Journal of Optical Communications and Networking;2023-08-11
5. In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging;IEEE Transactions on Components, Packaging and Manufacturing Technology;2022-07
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