PBTI under dynamic stress: From a single defect point of view
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5776767/5784429/05784502.pdf?arnumber=5784502
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1. Ultra-Fast Positive Gate Bias Stress (<100ns) to Understand the Hole Injection in Power p-GaN HEMTs;2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD);2023-05-28
2. Positive-Bias-Temperature-Instability Induced Random-Trap-Fluctuation Enhanced Physical Unclonable Functions on 14-nm nFinFETs;IEEE Electron Device Letters;2022-09
3. Anomalous PBTI Effects in N-Type Super Junction under High Gate Voltage Stress;Electronics;2022-04-25
4. Defect-Based Compact Modeling of Random Telegraph Noise;Noise in Nanoscale Semiconductor Devices;2020
5. Manufacturing Solutions;Dependable Multicore Architectures at Nanoscale;2017-08-30
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