TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test
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IEEE
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http://xplorestaging.ieee.org/ielx5/6235191/6241755/06241859.pdf?arnumber=6241859
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Fast in-line failure analysis of sub-micron-sized cracks in 3D interconnect technologies utilizing acoustic interferometry;Communications Engineering;2024-07-19
2. An end-to-end convolutional neural network for automated failure localisation and characterisation of 3D interconnects;Scientific Reports;2023-06-09
3. TSV Defects Classification with Machine Learning Approaches;2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA);2022-10-28
4. Fault Tolerance in 3D-ICs;Internet of Things;2018-12-14
5. References;Three-Dimensional Integrated Circuit Design;2017
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