L${}_{\text{2}}$min${}^{\text{2/2s}}$: Efficient Linear Reconstruction Filter for Incremental Delta-Sigma ADCs
Author:
Affiliation:
1. College of Science and Engineering, Hamad Bin Khalifa University, Doha, Qatar
2. State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics and FST-ECE, University of Macau, Macau, China
Funder
Qatar National Research Fund
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Signal Processing
Link
http://xplorestaging.ieee.org/ielx7/78/10040758/10254386.pdf?arnumber=10254386
Reference34 articles.
1. On the Signal Filtering Property of CT Incremental Sigma–Delta ADCs
2. Near-Optimal Decoding of Incremental Delta-Sigma ADC Output
3. Theory and Applications of Incremental<tex>$Delta Sigma $</tex>Converters
4. A 16 b Multi-Step Incremental Analog-to-Digital Converter With Single-Opamp Multi-Slope Extended Counting
5. A 4-μW Bandwidth/Power Scalable Delta-Sigma Modulator Based on Swing-Enhanced Floating Inverter Amplifiers
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