Design for velocity saturated, short-channel CMOS drivers with simultaneous switching noise and switching time considerations
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx1/4/11273/00535425.pdf?arnumber=535425
Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Simultaneous switching noise analysis using application specific device modeling;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2003-12
2. A compact multilayer IC package model for efficient simulation, analysis, and design of high-performance VLSI circuits;IEEE Transactions on Advanced Packaging;2003-11
3. Buffer delay change in the presence of power and ground noise;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2003-06
4. Simultaneous switching noise in on-chip CMOS power distribution networks;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2002-08
5. New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design;IEEE Transactions on Advanced Packaging;2000-05
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