Novel Multi-Level Coding and Architecture Enabling Fast Random Access for Flash Memory
Author:
Affiliation:
1. Kioxia Corporation,Institute of Memory Technology Research & Development,Japan
2. Kioxia Corporation,Memory Div.,Japan
3. Kioxia Corporation,Memory Development Strategy Div.,Japan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10536936/10536916/10536951.pdf?arnumber=10536951
Reference5 articles.
1. 13.5 A 128Gb 1b/Cell 96-Word-Line-Layer 3D Flash Memory to Improve Random Read Latency with tPROG=75µs and tR=4µs
2. A 1Tb 3b/Cell 3D-Flash Memory of more than 17Gb/mm2 bit density with 3.2Gbps interface and 205MB/s program throughput
3. Coding scheme for optimizing random I/O performance;Sharon
4. Construction of Random Input-Output Codes With Moderate Block Lengths
5. 7-Bit/2Cell (X3.5), 9-Bit/2Cell (X4.5) NAND Flash Memory: Half Bit technology
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