Transistor Sizing Scheme for DICE-Based Radiation-Resilient Latches
Author:
Affiliation:
1. University of Washington,Dept. of Electrical and Computer Engineering,Seattle,USA
2. Kyung Hee University,Dept. of Electronic Engineering,Yongin,Rep. of Korea
Funder
National Research Foundation of Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10049840/10049805/10049983.pdf?arnumber=10049983
Reference11 articles.
1. The effective drive current in CMOS inverters
2. Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node
3. A Fully Polarity-Aware Double-Node-Upset-Resilient Latch Design
4. Delta DICE: A Double Node Upset resilient latch
5. DONUT: A Double Node Upset Tolerant Latch
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1. Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023
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