A Review on Current-Steering DAC Design-Reference-Cited by-同舟云学术

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A Review on Current-Steering DAC Design

Published:2023-02-05 Issue: Volume: Page:
ISSN:
Container-title:2023 International Conference on Electronics, Information, and Communication (ICEIC)
language:
Short-container-title:

Author:

Lim Xian Yang¹,Lim Wu Cong¹,Teo Boon Chiat Terence¹,Navaneethan Venkadasamy¹,Tan Chong Boon¹,Utomo Nardi¹,Siek Liter¹,Alvandpour Atila¹

Affiliation:

1. Nanyang Technological University,School of Electrical and Electronic Engineering,Singapore,639798

Funder

MediaTek

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10049840/10049805/10049912.pdf?arnumber=10049912

Reference10 articles.

1. A 14-b, 100-MS/s CMOS DAC designed for spectral performance

2. SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters

3. A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < –61dB at 2.8 GS/s With DEMDRZ Technique

4. Static and Dynamic Performance Limitations for High Speed D/A Converters

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