Performance Optimization of Full Swing Adders For Future DSP & Machine Learning Applications Using 16 nm CMOS Process at High Temperatures
Author:
Affiliation:
1. SR University,Department of ECE,Warangal,India
2. Aurora’s Techn. & Research Institute,Department of ECE,Hyderabad,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9828864/9828869/09828910.pdf?arnumber=9828910
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