Design of an Efficient Reverse Carry Propagate Adder for Area Consumption on VLSI
Author:
Affiliation:
1. Veltech High Tech Dr Rangarajan Dr Sakuntala Engineering College,Department of Electronics and Communication Engineering,Chennai,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10547720/10547724/10547835.pdf?arnumber=10547835
Reference15 articles.
1. Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications
2. High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder
3. COREA: Delay- and Energy-Efficient Approximate Adder Using Effective Carry Speculation
4. A detailed scrutiny and reasoning on VLSI binary adder circuits and architectures;Priyadarshini;International Journal of Innovative Technology and Exploring Engineering,2019
5. A Review On N-Bit Ripple-Carry Adder, Carry-Select Adder And Carry-Skip Adder
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