Parasitic Inductance Design for Preventing Oscillatory False Triggering of Parallel-Connected GaN-FETs-Reference-Cited by-同舟云学术

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Parasitic Inductance Design for Preventing Oscillatory False Triggering of Parallel-Connected GaN-FETs

Published:2021-10-13 Issue: Volume: Page:
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Container-title:IECON 2021 – 47th Annual Conference of the IEEE Industrial Electronics Society
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Author:

Hatakenaka Yusuke,Umetani Kazuhiro,Ishihara Masataka,Hiraki Eiji,Tadano Hiroshi

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9588332/9589036/09589541.pdf?arnumber=9589541

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Mechanism Analysis and Oscillation Suppression of the False Triggering Oscillation for Parallel-Connected GaN Devices;IEEE Transactions on Power Electronics;2024-11

2. Parasitic Inductance Network Modeling Method for Power Module Inner Wirings Based on Inductance Matrix Measurement;2024 IEEE Applied Power Electronics Conference and Exposition (APEC);2024-02-25

3. Origin of Common Source Inductance in Power Device Packages with Kelvin Source Terminal;2023 IEEE Energy Conversion Congress and Exposition (ECCE);2023-10-29

4. Suppression Strategy for Oscillatory False Triggering Between Two paralleled GaN-HEMTs Based on Optimization of Parasitic Inductance;2023 IEEE Energy Conversion Congress and Exposition (ECCE);2023-10-29

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