Analysis of Power in SRAM Cell with Various Pull up, Pull down and Pass Gate Transistors
Author:
Affiliation:
1. CBE,Karunya Institute of Technology and Sciences,Department of ECE,IN
2. CBE,Karunya Institute of Technology and Sciences,Department of EEE,IN
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9787399/9787559/09787633.pdf?arnumber=9787633
Reference23 articles.
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3. LVTTL and SSTL IO Standards Based Energy efficient FSM Design on 16nm Utrascale Plus FPGA;pandey;12th International Conference on Computation Intelligence and Communication Networks,2020
4. Single-Event Transient Modeling in a 65-nm Bulk CMOS Technology Based on Multi-Physical Approach and Electrical Simulations
5. Compact analytical model to extract write static noise margin (WSNM) for SRAM cell at 45-nm and 65-nm nodes;dasgupta;IEEE Transactions on Semiconductor Manufacturing,2017
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