7.5 A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm2and 6T HBST-TRAM-Based 2D Data-Reuse Architecture-Reference-Cited by-同舟云学术

7.5 A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm2and 6T HBST-TRAM-Based 2D Data-Reuse Architecture

Published:2019-02 Issue: Volume: Page:
ISSN:
Container-title:2019 IEEE International Solid- State Circuits Conference - (ISSCC)
language:
Short-container-title:

Author:

Yue Jinshan,Liu Ruoyang,Sun Wenyu,Yuan Zhe,Wang Zhibo,Tu Yung-Ning,Chen Yi-Ju,Ren Ao,Wang Yanzhi,Chang Meng-Fan,Li Xueqing,Yang Huazhong,Liu Yongpan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8656625/8662285/08662360.pdf?arnumber=8662360

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