19.5 Digital Leakage Compensation for a Low-Power and Low-Jitter 0.5-to-5GHz PLL in 10nm FinFET CMOS Technology-Reference-Cited by-同舟云学术

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19.5 Digital Leakage Compensation for a Low-Power and Low-Jitter 0.5-to-5GHz PLL in 10nm FinFET CMOS Technology

Published:2019-02 Issue: Volume: Page:
ISSN:
Container-title:2019 IEEE International Solid- State Circuits Conference - (ISSCC)
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Author:

Fan Yongping,Xiang Bo,Zhang Dan,Ayers James S.,Shen Kuan-Yueh James,Mezhiba Andrey

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8656625/8662285/08662526.pdf?arnumber=8662526

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Wideband and Low Reference Spur PLL with Clock Feedthrough Suppressed and Low Current Mismatch Charge Pump and Symmetrical CML Divider;Electronics;2023-10-07

2. Ring-VCO-based phase-locked loops for clock generation – design considerations and state-of-the-art;Chip;2023-06

3. A 7.6–12.3 GHz wide‐band PLL with an ultra low reference spur −81.1 dBc in 0.13 μm CMOS technology;International Journal of Circuit Theory and Applications;2023-03-21

4. Design and Analysis of the Self-Biased PLL with Adaptive Calibration for Minimum of the Charge Pump Current Mismatch;Electronics;2022-07-07

5. Design of 0.6v 0.01mm2 Sub Sampling PLL Based On Dynamic Double Loops;The 2022 5th International Conference on Electronics, Communications and Control Engineering;2022-03-25

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