14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S

Author:

Tsai Tsung-Hsien,Yuan Min-Shueh,Chang Chih-Hsien,Liao Chia-Chun,Li Chao-Chieh,Staszewski Robert Bogdan

Publisher

IEEE

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Tapped delay line for compact time-to-digital converter on UltraScale FPGA and its coding method;Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment;2023-11

2. 5.7 ps Resolution Time-to-Digital Converter Implementation Using Routing Path Delays;Electronics;2023-08-17

3. Two-Stage Clock-Free Time-to-Digital Converter Based on Vernier and Tapped Delay Lines in FPGA Device;Electronics;2021-09-07

4. Multi-phase low-noise digital ring oscillators with sub-gate-delay resolution;AEU - International Journal of Electronics and Communications;2018-02

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