5.7 ps Resolution Time-to-Digital Converter Implementation Using Routing Path Delays

Abstract

A tapped delay line (TDL)-based time-to-digital converter (TDC) implemented on an FPGA (Field Programmable Gate Array) is sensitive to nonlinearities because of significant variations in the delay of the delay elements. Most of the nonlinearity of FPGA-based TDCs comes from the routing of the design. It is promising to realize TDCs using internal routing resources available in FPGAs, as these devices contain a lot of routing resources and are resistant to voltage and temperature changes. This work implements and tests a TDC based on a series of counters driven by a variable delay line that exploits the internal routing resources available in the FPGA as delay elements. A manual placement and routing technique that results in greater resolution and linearity is proposed. The time-interleaving concept is used to improve the resolution of the TDC. A measurement matrix with 512 and 1024 parallel counters is implemented on a Zynq Evaluation and Development (ZED) board. The result of the 1024-unit TDC showed that a dynamic range of 93.6 ns can be measured using a 4-bit coarse gray code counter running at a reference frequency of 171 MHz, and a resolution of 5.7 ps is achieved. The implemented TDC is low-cost, has a fast time to market, and it benefits from the abundant routing resources in the FPGA.