23.8 A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4-Reference-Cited by-同舟云学术

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23.8 A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4

Published:2017-02 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Choi Woojun,Kim Taewoong,Shim Jongjoo,Kim Hyungsoo,Han Gunhee,Chae Youngcheol

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7866667/7870233/07870431.pdf?arnumber=7870431

Cited by 16 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 24-Gb/s MIPI C-/D-PHY Receiver Bridge Chip With Phase Error Calibration Supporting FPGA-Based Frame Grabber;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-04

2. CASA: An Energy-Efficient and High-Speed CAM-based SMEM Seeding Accelerator for Genome Alignment;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

3. A 6-Gb/s PAM-3 Transceiver With Background Time-Varying Offset Sensing and Compensation;IEEE Solid-State Circuits Letters;2023

4. Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-08

5. A 64-Gb/s Ground-Referenced Signaling PAM-4 Transmitter with Switched-Capacitor Charge Pump Driver;2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC);2022-07-05

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