A 6.4Gb/s CMOS SerDes core with feedforward and decision-feedback equalization
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/9995/32118/01493869.pdf?arnumber=1493869
Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A power‐efficient current‐integrating hybrid for full‐duplex communication over chip‐to‐chip interconnects;International Journal of Circuit Theory and Applications;2022-07-27
2. 8 mW 1.65-Gbps continuous-time equalizer with clock attenuation detection for digital display interface;Analog Integrated Circuits and Signal Processing;2009-10-11
3. An 11.75-Gb/s combined decision feedback equalizer and clock data recovery circuit in 0.18-μm CMOS;ESSCIRC 2007 - 33rd European Solid-State Circuits Conference;2007-09
4. Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs;IEEE Custom Integrated Circuits Conference 2006;2006-09
5. A 2.5- to 3.5-Gb/s Adaptive FIR Equalizer With Continuous-Time Wide-Bandwidth Delay Line in 0.25-$muhbox m$CMOS;IEEE Journal of Solid-State Circuits;2006-08
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