Author:
Kim Kyu-Young,Lee Woo-Kwan,Yoo Jae-Tack,Kim Soo-Won
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Reference13 articles.
1. http://www.hdmi.org .
2. Johns, D. A., & Essig, D. (1997). Integrated circuits for data transmission over twisted-pair channels. IEEE Journal of Solid-State Circuits, 32(3), 398–406.
3. Gotoh, K., Tamura, H., Takauchi, H., Cheung, T.S., Gai, W., Koyanagi, Y., et al. (1999). A 2B parallel 1.25-Gb/s interconnect I/O interface with self-configurable link and plesiochronous clocking. IEEE International Solid-State Circuits Conference of Digital Technology Papers, pp. 180–181.
4. Sorna, M., Beukerna, T., Selander, K., Zier, S., Ji, B., Murfet, P., et al. (2005). A 6.4 Gb/s CMOS SerDes core with feedforward and decision-feedback. IEEE International Solid-State Circuits Conference of Digital Technology Papers, pp. 62–63.
5. Stojanovic, V., Ho, A., Garlepp, B. W., Chen, F., Wei, J., Tsang, G., et al. (2005). Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery. IEEE Journal of Solid-State Circuits, 40(4), 1012–1026.