10.5 A 5.9pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS-Reference-Cited by-同舟云学术

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10.5 A 5.9pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS

Published:2015-02 Issue: Volume: Page:
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Container-title:2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers
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Author:

Dokania Rajeev,Kern Alexandra,He Mike,Faust Adam,Tseng Richard,Weaver Skyler,Yu Kai,Bil Christiaan,Liang Tao,O'Mahony Frank

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7054075/7062838/07062987.pdf?arnumber=7062987

Cited by 19 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-08

2. A 16 Gb/s serial link transceiver with active inductor based CTLE and 3-tap DFE in 12-nm FinFET CMOS;Microelectronics Journal;2024-06

3. A 20-Gb/s Jitter-Tolerance-Enhanced Baud-Rate CDR Circuitwith One-Tap DFE;2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA);2024-04-22

4. A Low-Jitter Phase Detection Technique With Asymmetric Weights in Multi-Level Baud-Rate CDR;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

5. A 0.061-pJ/b/dB 28-Gb/s Gradient-Based Maximum Eye Tracking CDR With 2-Tap DFE Adaptation in 28-nm CMOS;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-11

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