A 0.061-pJ/b/dB 28-Gb/s Gradient-Based Maximum Eye Tracking CDR With 2-Tap DFE Adaptation in 28-nm CMOS-Reference-Cited by-同舟云学术

A 0.061-pJ/b/dB 28-Gb/s Gradient-Based Maximum Eye Tracking CDR With 2-Tap DFE Adaptation in 28-nm CMOS

Published:2023-11 Issue:11 Volume:70 Page:3998-4002
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Lee Sanghee¹^ORCID,Kang Byungjun¹^ORCID,Rhee Woogeun²^ORCID,Jeong Deog-Kyoon¹^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering and the Inter University Semiconductor Research Center, Seoul National University, Seoul, South Korea

2. School of Integrated Circuits, Tsinghua University, Beijing, China

Funder

Institute of Information and Communications Technology Planning and Evaluation IITP Grant funded by the Korea Government

Samsung Electronics Company Ltd.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/10299398/10130084.pdf?arnumber=10130084

Reference9 articles.

1. A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm

2. A 0.36 pJ/bit, 0.025 mm ${}^{\text{2}}$ , 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology

3. A 28-Gb/s Receiver With Self-contained Adaptive Equalization and Sampling Point Control Using Stochastic Sigma-Tracking Eye-Opening Monitor

4. Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric

5. A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler

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