8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring-Reference-Cited by-同舟云学术

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8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring

Published:2016-01 Issue: Volume: Page:
ISSN:
Container-title:2016 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Wilson John M.,Fojtik Matthew R.,Poulton John W.,Chen Xi,Tell Stephen G.,Greer Thomas H.,Gray C. Thomas,Dally William J.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7405163/7417881/7417954.pdf?arnumber=7417954

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Bonanza Mine: an Ultra-Low-Voltage Energy-Efficient Bitcoin Mining ASIC;2022 IEEE International Solid- State Circuits Conference (ISSCC);2022-02-20

2. On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications;IEEE Journal of Solid-State Circuits;2021-11

3. A charge recycling stacked I/O in standard CMOS technology for wide TSV data bus;IEICE Electronics Express;2020-05-25

4. Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications;2019 IEEE Custom Integrated Circuits Conference (CICC);2019-04

5. A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling;IEEE Journal of Solid-State Circuits;2017-04

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