A charge recycling stacked I/O in standard CMOS technology for wide TSV data bus-Reference-Cited by-同舟云学术

A charge recycling stacked I/O in standard CMOS technology for wide TSV data bus

Published:2020-05-25 Issue:10 Volume:17 Page:20200112-20200112
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Yoshikawa Takefumi¹,Iwata Tatsuya¹,Shibazaki Junji¹,Muroga Sho²,Ikeda Hiroaki³

Affiliation:

1. Dept. of Electrical and Computer Engineering, Toyama Prefectural University

2. Graduate School of Engineering Science, Akita University

3. Graduate School of Science, Technology and Innovation, Kobe University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/17/10/17_17.20200112/_pdf

Reference30 articles.

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2. [2] M.T. Bohr and I.A. Young: “CMOS scaling trends and beyond,” IEEE Micro 37 (2017) 20 (DOI: 10.1109/MM.2017.4241347).

3. [3] J. Meindl, et al.: “Limits on silicon nanoelectronics for terascale integration,” Science, 293 (2001) 2044 (DOI: 10.1126/science.293.5537.2044).

4. [4] S. Borkar, “Design challenges of technology scaling,” IEEE Micro 19 (1999) 23 (DOI: 10.1109/40.782564)

5. [5] E.F. Rent: “Microminiature packaging logic block to pin ratio,” Memoranda 28 (1960).

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