A 94GHz Locking Hysteresis-Assisted and Tunable CML Static Divider in 65nm SOI CMOS
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4497158/4523032/04523256.pdf?arnumber=4523256
Cited by 25 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A 24.4~39.6 GHz Wide Locking Range Divide-by-4 Injection-Locked Frequency Divider With High Harmonic Rejection Ratio;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-06
2. A Broadband and High Speed CML Divider with Inductor Peaking in 40-nm SMIC;2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT);2022-10-25
3. Injection-Locking Techniques for CMOS Millimeter-Wave and Terahertz Signal Generation;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-07
4. Design of an Inductor-Less 72-GHz 2:1 CMOS CML Frequency Divider With Dual-Core VCO;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-06
5. A 0.35-mW 70-GHz Self-Resonant E-TSPC Frequency Divider With Backgate Adjustment;IEEE Transactions on Microwave Theory and Techniques;2022-04
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