Design of an Inductor-Less 72-GHz 2:1 CMOS CML Frequency Divider With Dual-Core VCO-Reference-Cited by-同舟云学术

Design of an Inductor-Less 72-GHz 2:1 CMOS CML Frequency Divider With Dual-Core VCO

Published:2022-06 Issue:6 Volume:69 Page:2752-2756
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Chou Ethan¹^ORCID,Iotti Lorenzo¹,Niknejad Ali¹^ORCID

Affiliation:

1. Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA

Funder

Defense Advanced Research Projects Agency through the T-MUSIC Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/9786589/09758065.pdf?arnumber=9758065

Reference17 articles.

1. Understanding dynamic behavior of mm-wave CML divider with injection-locking concept

2. Modeling and design of a 0.8-30 GHz tunable inductor-iess divide-by-2 frequency divider with digital frequency calibration;gao;Proc IEEE Int Midwest Symp Circuits Syst (MWSCAS),2015

3. A Comprehensive Delay Model for CMOS CML Circuits

4. Analysis and design of injection-locked LC dividers for quadrature generation

5. A unified model for injection-locked frequency dividers

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