A 14b 100MS/s digitally self-calibrated pipelined ADC in 0.13/spl mu/m CMOS
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/11149/35738/01696123.pdf?arnumber=1696123
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Recent Advances and Trends in High-Performance Embedded Data Converters;High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing;2014-07-24
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3. Low-Power Pipelined A/D Conversion;Analog Circuit Design;2011-09-04
4. High-Resolution and Wide-Bandwidth CMOS Pipeline AD Converters;Analog Circuit Design;2009-10-21
5. Single-Reference Foreground Calibration of High-Resolution, High-Speed Pipeline ADCs;Circuits, Systems, and Signal Processing;2009-01-10
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