A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS-Reference-Cited by-同舟云学术

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A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS

Published:2018-02 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE International Solid - State Circuits Conference - (ISSCC)
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Author:

Ho Cheng-Ru,Chen Mike Shuo-Wei

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8304413/8310156/08310350.pdf?arnumber=8310350

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A high-pass shaped LMS algorithm based predistortion technique for fractional-N BB-DPLLs;Microelectronics Journal;2024-04

2. 10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

3. A (0.75–1.13) mW and (2.4–5.2) ps RMS Jitter Integer-N-Based Dual-Loop PLL for Indoor and Outdoor Positioning in 28-nm FD-SOI CMOS Technology;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-10

4. A 1.2V Low-Power Multi-Band Mixing Frequency Synthesizer for FDD System;2023 IEEE MTT-S International Wireless Symposium (IWS);2023-05-14

5. A Deep Reinforcement Learning Framework for High-Dimensional Circuit Linearization;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-09

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