1. Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12
2. Polynomial Formal Verification of Approximate Adders with Constant Cutwidth;2024 IEEE European Test Symposium (ETS);2024-05-20
3. Polynomial Formal Verification of Sequential Circuits;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25
4. Complete and Efficient Verification for a RISC-V Processor Using Formal Verification;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25
5. Automated Polynomial Formal Verification: Human-Readable Proof Generation;2023 IEEE International Symposium on Smart Electronic Systems (iSES);2023-12-18