Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification-Reference-Cited by-同舟云学术

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Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification

Published:2024-06-12 Issue: Volume: Page:502-506
ISSN:
Container-title:Proceedings of the Great Lakes Symposium on VLSI 2024
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Author:

Qayyum Khushboo¹^ORCID,Kole Abhoy²^ORCID,Datta Kamalika³^ORCID,Hassan Muhammad⁴^ORCID,Drechsler Rolf⁴^ORCID

Affiliation:

1. Computer Science, University of Bremen /DFKI GmbH, Germany

2. DFKI GmbH, Germany

3. Institute of Computer Science, University of Bremen /DFKI GmbH, Germany

4. University of Bremen /DFKI GmbH, Germany

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3649476.3658766

Reference23 articles.

1. L. Amaru P-E Gaillardon and G. D. Micheli. 2014. Majority Inverter Graph: A novel data-structure and algorithms for efficient logic optimization. DAC.

2. B. Becker R. Drechsler and R. Enders. 1997. On the representational power of bit-level and word-level decision diagrams. ASP-DAC.

3. K. Bhunia A. Deb K. Datta M. Hassan S. Shirinzadeh and R. Drechsler. 2023. ReSG: A Data Structure for Verification of Majority based In-Memory Computing on ReRAM Crossbars. TECS.

4. Graph-based algorithms for boolean function manipulation. Computers;Bryant E.;IEEE Transactions on.,1986

5. R. E. Bryant and Y. Chen. 2001. Verification of arithmetic circuits using binary moment diagrams. STTT.

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