A Formal Model of Clock Domain Crossing and Automated Verification of Time-Triggered Hardware
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4401966/4401967/04402004.pdf?arnumber=4402004
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Generic CDC Modeling for Data Stability Verification;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04
2. Enabler-Based Synchronizer Model for Clock Domain Crossing Static Verification;Lecture Notes in Electrical Engineering;2016
3. FlexRay for Avionics: Automatic Verification with Parametric Physical Layers;Infotech@Aerospace 2012;2012-06-19
4. Automated verification and refinement for physical-layer protocols;Formal Aspects of Computing;2011-05
5. Complete Formal Hardware Verification of Interfaces for a FlexRay-Like Bus;Computer Aided Verification;2011
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