Design Of High-Speed Vedic Multiplier Using Urdhva Tiryakbhyam Sutra-Reference-Cited by-同舟云学术

Design Of High-Speed Vedic Multiplier Using Urdhva Tiryakbhyam Sutra

Published:2022-02-16 Issue: Volume: Page:
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Container-title:2022 First International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT)
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Author:

Singh Pallavi¹,Dinendra C.¹,Hemanth R. J.¹,Vivek N. Mitra¹

Affiliation:

1. Hindustan Institute of Technology and Science,Department of Electronics and Communication,Chennai,India

Publisher

IEEE

Link

Reference8 articles.

2. An area efficient 64-bit square root carry-select adder for low power applications;he;IEEE International Symposium on Circuits and Systems,2005

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