Optimal Global Interconnects for Networks-on-Chip in Many-Core Architectures

Author:

Balakrishnan A.,Naeemi A.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Use of current-mode and voltage-mode receivers together for on-chip multipoint-to-multipoint data transmission across global interconnects;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

2. Investigating the role of interconnect surface roughness towards the design of power‐aware network on chip;IET Computers & Digital Techniques;2018-09-19

3. Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects;Journal of Circuits, Systems and Computers;2016-07-22

4. A Systematic Design Methodology for Low-Power NoCs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2014-12

5. Interconnect Network Analysis of Many-Core Chips;IEEE Transactions on Electron Devices;2011-09

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