Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects

Abstract

On-chip global interconnects are becoming speed and power bottlenecks in state-of-the-art chips. Low-swing signaling is used to improve delay performance and reduce power consumption. This paper first performs a delay analysis for different low-swing circuits based on the Asymptotic Waveform Evaluation (AWE). In addition, new delay metrics are presented and analyzed. The new delay metrics demonstrate that optimal designs can be obtained in low-swing signaling. To verify our analysis, a simulation environment is established. The simulation results indicate that the optimal designs can increase the 3[Formula: see text]dB bandwidth of a wire by more than 40% in resistively driven or capacitively driven 10[Formula: see text]mm global links. Thus, these optimal design methods can effectively improve the bandwidth of global wires.